However, cross-point array memristors are suppressed by the sneak current issue, in which the current flows through the unselected cells, and this can lead to low energy efficiency and excessive noise problems 8, 9.

Two-terminal memristors, which use conducting filaments, phase change materials, and protonic layers between two electrodes, have been proposed for artificial synaptic devices through the various neural functions and geometric advantages 5, 6, 7. Inspired by biological neurons and synapses, neural systems have many distinctive advantages, including massive parallelism, power-efficiency, storage/computation combination, and self-learning 3, 4. Neural systems have been actively investigated to replace traditional Boolean logic and von Neumann architecture 1, 2. Therefore, the proposed organic–inorganic hybrid EDL is expected to be useful for implementing an extremely compact neural architecture system.

Synaptic behaviours such as the hysteresis window and excitatory post-synaptic current (EPSC) variations were evaluated for different DC gate voltage sweep ranges and different AC gate spike stimuli, respectively. This demonstrated good inverter action and responded to the square-wave input signals. A resistor-loaded inverter was constructed by connecting an IGZO EDLT with a load resistor (400 MΩ) in series. The on/off current ratio, subthreshold voltage swing, and the field-effect mobility of the fabricated IGZO EDL transistors (EDLTs) exhibited excellent electrical properties of 1.80 × 10 7, 96 mV/dec, and 3.73 cm 2/V This technique achieved ion-conduction from the chitosan electrolyte to the In-Ga-Zn oxide (IGZO) channel layer.

The Ta 2O 5 high- k dielectric layer with high chemical resistance, thermal stability, and mechanical strength enables CMOS-compatible patterning processes on biocompatible organic polymer chitosan electrolytes. Bio-inspired synaptic transistors with excellent electrical stability were fabricated using the proposed hybrid EDL for the gate dielectric layer. This study proposes a hybrid electric double layer (EDL) with complementary metal-oxide semiconductor (CMOS) process compatibility by stacking a chitosan electrolyte and a Ta 2O 5 high- k dielectric thin film.

Cmos transistor